dual epad? ultra micropower operational amplifier a dvanced l inear d evices, i nc. ald2726e/ald2726 general description the ald2726e/ald2726 is a dual monolithic rail-to-rail precision cmos operational amplifier with integrated user programmable epad (electri- cally programmable analog device) based offset voltage adjustment. the ald2726e/ald2726 is a dual version of the ald1726e/ald1726 opera- tional amplifier. each ald2726e/ald2726 operational amplifier features individual, user-programmable offset voltage trimming resulting in signifi- cantly enhanced total system performance and user flexibility. epad technology is an exclusive ald design which has been refined for analog applications where precision voltage trimming is necessary to achieve a desired performance. it utilizes cmos fets as in-circuit elements for trimming of offset voltage bias characteristics with the aid of a personal computer under software control. once programmed, the set parameters are stored indefinitely. epad offers the circuit designer a convenient and cost-effective trimming solution for achieving the very highest amplifier/ system performance. the ald2726e/ald2726 dual operational amplifier features rail-to-rail input and output voltage ranges, tolerance to overvoltage input spikes of 300mv beyond supply rails, capacitive loading up to 25pf, extremely low input currents of 0.01pa typical, high open loop voltage gain, useful bandwidth of 700khz, slew rate of 0.7v/ m s, and low typical supply current of 50 m a for both amplifiers. key features ? epad ( electrically programmable analog device) ? user programmable v os trimmer ? computer-assisted trimming ? rail-to-rail input/output ? compatible with standard epad programmer ? each amplifier v os can be trimmed to a different vos level ? high precision through in-system circuit trimming ? reduces or eliminates v os , psrr, cmrr and tcv os errors ? system level calibration capability ? application specific programming mode ? in-system programming mode ? electrically programmable to compensate for external component tolerances ? 0.01pa input bias current and 35 m v input offset voltage ? 1v to 5v operation applications ? sensor interface circuits ? transducer biasing circuits ? capacitive and charge integration circuits ? biochemical probe interface ? signal conditioning ? portable instruments ? high source impedance electrode amplifiers ? precision sample and hold amplifiers ? precision current to voltage converter ? error correction circuits ? sensor compensation circuits ? precision gain amplifiers ? periodic in-system calibration ? system output level shifter pin configuration ordering information operating temperature range -55 c to +125 c0 c to +70 c0 c to +70 c 14-pin 14-pin 14-pin cerdip small outline plastic dip package package (soic) package ald2726e db ald2726e sb ald2726e pb ald2726 db ald2726 sb ald2726 pb * contact factory for industrial temperature range benefits ? eliminates manual and elaborate system trimming procedures ? remote controlled automated trimming ? in-system programming capability ? no external components ? no internal clocking noise source ? simple and cost effective ? small package size ? extremely small total functional volume size ? low system implementation cost ? micropower 1 2 3 4 5 6 7 11 12 13 14 8 9 10 top view db, pb, sb package ve 2a ve 1a v - n/c ve 2b ve 1b out b out a +in a -in a +in b -in b n/c v + ? 1998 advanced linear devices, inc. 415 tasman drive, sunnyvale, california 94089 -1706 tel: (408) 747-1155 fax: (408) 747-1286 http://www.aldinc.com
2 advanced linear devices ald2726e/ald2726 functional description of ald2726 the ald2726 is pre-programmed at the factory under standard operating conditions for minimum equivalent input offset voltage. the ald2726 offers similar programmable features as the ald2726e, but with more limited offset voltage program range. it is intended for standard operational amplifier applications where little or no electrical programming by the user is necessary. user programmable v os feature each ald2726e/ald2726 has four additional pins, compared to a conventional dual operational amplifier which has eight pins. these four additional pins are named ve1a, ve2a for op amp a and ve1b, ve2b for op amp b. each of these pins ve1a, ve2a, ve1b, ve2b (represented by vexx) are connected to a separate, internal offset bias circuit. vexx pins have initial internal bias voltage values of approximately 1 to 2 volts. the voltage on these pins can be programmed using the ald e100 epad programmer and the appropriate adapter module. the useful programming range of voltages on vexx pins are 1 volt to 3 volts. vexx pins are programming pins, used during electrical programming mode to inject charge into the internal epads. increasing voltage on ve1a/ve1b increases the offset volt- age whereas increasing voltage on ve2a/ve2b decreases the offset voltage of op amp a and op amp b, respectively. the injected charge is then permanently stored. after pro- gramming, vexx pins must be left open in order for these voltages to remain at the programmed levels. during programming, voltages on vexx pins are increased incrementally to program the offset voltage of the operational amplifier to the desired v os . note that desired v os can be any value within the offset voltage programmable ranges, and can be either equal zero, a positive value or a negative value. this v os value can also be reprogrammed to a different value at a later time, provided that the useful ve1x or ve2x programming voltage range has not been exceeded. vexx pins can also serve as capacitively coupled input pins. internally, ve1 and ve2 are programmed and connected differentially. temperature drift effects between the two internal offset bias circuits cancel each other and introduce less net temperature drift coefficient change than offset voltage trimming techniques such as offset adjustment with an external trimmer potentiometer. while programming, v+, ve1 and ve2 pins may be alter- nately pulsed with 12v (approximately) pulses generated by the epad programmer. in-system programming requires the ald2721e application circuit to accommodate these programming pulses. this can be accomplished by adding resistors at certain appropriate circuit nodes. for more information, see application note an1700. functional description the ald2726e/ald2726 utilizes epads as in-circuit elements for trimming of offset voltage bias characteristics. each ald2726e/ald2726 operational amplifier has a pair of epad-based circuits connected such that one circuit is used to adjust v os in one direction and the other circuit is used to adjust v os in the other direction. while each of the basic epad devices is monotonically adjustable, the v os of the ald2721e can be adjusted many times in both directions. once programmed, the set v os levels are stored permanently, even when the device is removed. functional description of ald2726e the ald2726e is pre-programmed at the factory under standard operating conditions for minimum equivalent input offset voltage. it also has a guaranteed offset voltage program range, which is ideal for applications that require electrical offset voltage programming. the ald2726e is an operational amplifier that can be trimmed stand-alone, with user application-specific programming or in- system programming conditions. user application-specific circuit programming refers to a situation where the total input offset voltage of the ald2726e can be trimmed with the actual intended operating conditions. take the example of an application circuit that uses + 1v and -1v power supplies, an operational amplifier input biased at +1v, and an average operating temperature at +85 c; the circuit can be wired up to these conditions within an environ- mental chamber with the ald2726e inserted into a test socket while it is being electrically trimmed. any error in v os due to these bias conditions can be automatically zeroed out. the total v os error is now limited only by the adjustable range and the stability of v os , and the input noise voltage of the operational amplifier. this total input offset voltage, v ost, now includes v os , as v os is traditionally specified; plus the v os error contributions from psrr, cmrr, tcv os , and noise. typically, v ost ranges approximately 35 m v for the ald2726e. in-system programming refers to the condition where the epad adjustment is made after the ald2726e has been inserted into a circuit board. in this case, the circuit design must provide for the ald2726e to operate in both normal mode and in programming mode. one of the benefits of in-system programming is that not only the ald276e offset voltage from operating bias conditions has been accounted for, any residual errors introduced by other circuit components, such as resistor or sensor induced voltage errors, can also be programmed and corrected. in this way, the in-system circuit output can be adjusted to a desired level eliminating need for another trimming function.
ald2726e/ald2726 advanced linear devices 3 supply voltage, v + 13.2v differential input voltage range -0.3v to v + +0.3v power dissipation 600 mw operating temperature range pb,sb package 0 c to +70 c db package -55 c to +125 c storage temperature range -65 c to +150 c lead temperature, 10 seconds +260 c absolute maximum ratings operating electrical characteristics t a = 25 o c v s = 2.5v unless otherwise specified 2726e 2726 parameter symbol min typ max min typ max unit test conditions supply voltage v s 1.0 5.0 1.0 5.0 v v + 2.0 10.0 2.0 10.0 v single supply initial input offset voltage 1 v os i 35 100 50 150 m vr s 100k w offset voltage program range 2 d v os 7 15 0.7 4mv programmed input offset v os 50 100 50 150 m v at user specified voltage error 3 target offset voltage total input offset voltage 4 v ost 50 100 50 150 m v at user specified target offset voltage input offset current 5 i os 0.01 10 0.01 10 pa t a = 25 c 240 240 pa 0 c t a +70 c input bias current 5 i b 0.01 10 0.01 10 pa t a = 25 c 240 240 pa 0 c t a +70 c input voltage range 6 v ir -0.3 5.3 -0.3 5.3 v v + = +5v -2.8 +2.8 -2.8 +2.8 v v s = 2.5v input resistance r in 10 14 10 14 w input offset voltage drift 7 tcv os 77 m v/ cr s 100k w initial power supply psrr i 90 90 db r s 100k w rejection ratio 8 initial common mode cmrr i 90 90 db r s 100k w rejection ratio 8 large signal voltage gain a v 15 100 15 100 v/mv r l =100k w 10 10 v/mv 0 c t a +70 c v o low 0.001 0.01 0.001 0.01 v r l =1m w v =5v output voltage range v o high 4.99 4.999 4.99 4.999 v 0 c t a +70 c v o low -2.48 -2.40 -2.48 -2.40 v r l =100k w v o high 2.40 2.48 2.40 2.48 v 0 c t a +70 c output short circuit current i sc 200 200 m a * notes 1 through 9, see section titled "definitions and design notes".
4 advanced linear devices ald2726e/ald2726 operating electrical characteristics (cont'd) t a = 25 o c v s = 2.5v unless otherwise specified 2726e 2726 parameter symbol min typ max min typ max unit test conditions supply current i s 50 80 50 80 m av in = 0v no load power dissipation p d 400 400 m wv s = 2.5v input capacitance c in 11 pf maximum load capacitance c l 25 25 pf equivalent input noise voltage e n 55 55 nv/ ? hz f = 1khz equivalent input noise current i n 0.6 0.6 fa/ ? hz f =10hz bandwidth b w 200 200 khz slew rate s r 0.1 0.1 v/ m sa v = +1 r l = 100k w rise time t r 1.0 1.0 m sr l = 100k w overshoot factor 20 20 % r l =100k w c l =25pf settling time t s 10 10 m s 0.1% a v = -1 r l = 100k w c l = 25pf channel separation cs 140 140 db a v =100 * notes 1 through 9, see section titled "definitions and design notes". t a = 25 o c v s = 2.5v unless otherwise specified 2726e 2726 parameter symbol min typ max min typ max unit test conditions average long term input offset d v os 0.02 0.02 m v/ voltage stability 9 d time 1000 hrs initial ve voltage ve1 i , ve2 i 1.5 1.8 v programmable change of d ve1, d ve2 0.5 1.0 0.5 v ve range programmed ve voltage error e(ve1-ve2) 0.1 0.1 % ve pin leakage current i eb -5 -5 m a
ald2726e/ald2726 advanced linear devices 5 t a = 25 o c v s = 1.0v unless otherwise specified 2726e 2726 parameter symbol min typ max min typ max unit test conditions initial power supply psrr i 80 80 db r s 100k w rejection ratio 8 initial common mode cmrr i 80 80 db r s 100k w rejection ratio 8 large signal voltage gain a v 50 50 v/mv r l = 1m w output voltage range v o low -0.95 -0.9 -0.95 -0.9 v r l = 1m w v o high 0.9 0.95 0.9 0.95 bandwidth b w 0.2 0.2 mhz slew rate s r 0.1 0.1 v/ m sa v = +1, c l = 25pf v s = 2.5v -55 c t a +125 c unless otherwise specified 2726e 2726 parameter symbol min typ max min typ max unit test conditions initial input offset voltage v os i 0.7 0.7 mv r s 100k w input offset current i os 2.0 2.0 na input bias current i b 2.0 2.0 na initial power supply psrr i 85 85 db r s 100k w rejection ratio 8 initial common mode cmrr i 83 83 db r s 100k w rejection ratio 8 large signal voltage gain a v 10 50 10 50 v/mv r l = 1m w output voltage range v o low -2.40 -2.25 -2.40 -2.25 v v o high 2.25 2.40 2.25 2.40 v r l = 1m w
6 advanced linear devices ald2726e/ald2726 typical performance characteristics output voltage swing as a function of supply voltage supply voltage (v) 0 1 2 3 4 7 6 5 6 5 4 3 2 1 output voltage swing (v) 25 c t a +125 c r l = 100k input bias current as a function of ambient temperature ambient temperature ( c) 100 10 1.0 0.01 0.1 input bias current (pa) 100 -25 0 75 125 50 25 -50 1000 v s = 2.5v open loop voltage gain as a function of supply voltage and temperature supply voltage (v) 1000 100 10 1 open loop voltage gain (v/mv) 0 2 4 6 55 c t a +125 c r l = 100k 8 supply current as a function of supply voltage supply voltage (v) 160 120 40 80 0 supply current ( a) 0 1 2 3 4 5 6 t a = -55 c -25 c +25 c +70 c +125 c inputs grounded output unloaded open loop voltage gain as a function of frequency frequency (hz) 1 10 100 1k 10k 1m 10m 100k 120 100 80 60 40 20 0 -20 open loop voltage gain (db) v s = 2.5v t a = 25 c 90 0 45 180 135 phase shift in degrees adjustment in input offset voltage as a function of change in ve1 and ve2 change in input offset voltage ? v os (mv) 0.0 0.25 0.5 0.75 1.0 1.25 1.50 -10 -8 -6 -4 -2 0 2 4 6 8 10 ve1 ve2 change in ve1 and ve2 (v)
ald2726e/ald2726 advanced linear devices 7 typical performance characteristics common mode input voltage range as a function of supply voltage supply voltage (v) common mode input voltage range (v) 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 t a = 25 c -2500 -2000 -1500 -1000 -500 0 500 1000 1500 2000 2500 total input offset voltage ( v) 100 80 60 40 20 0 distribution of total input offset voltage before and after epad programming example b: v ost after epad programming v ost target = -750 v example a: v ost after epad programming v ost target = 0.0 v v ost before epad programming percentage of units (%) large - signal transient response v s = 1.0v t a = 25 c r l = 100k c l = 25pf 2v/div 500mv/div 10 s/div open loop voltage gain as a function of load resistance 10m load resistance ( ) 10k 100k 1m 1000 100 10 1 open loop voltage gain (v/mv) v s = 2.5v t a = 25 c small - signal transient response 100mv/div 50mv/div 10 s/div v s = 2.5v t a = 25 c r l = 100k c l = 25pf large - signal transient response 2v/div 10 s/div 5v/div v s = 2.5v t a = 25 c r l = 100k c l = 25pf
8 advanced linear devices ald2726e/ald2726 0 1 2 3 4 5 6 789 10 500 400 300 200 100 0 equivalent input offset voltage due to change in supply voltage ( v) two examples of equivalent input offset voltage due to change in supply voltage vs. supply voltage supply voltage (v) psrr = 80 db example b: v os epad programmed at v supply = +8v example a: v os epad programmed at v supply = +5v -5 -4 -3 -2 -1 0 1 2345 common mode voltage (v) 500 400 300 200 100 0 equivalent input offset voltage due to change in common mode voltage ( v) example a: v os epad programmed at v in = 0v example b: v os epad programmed at v in = -4.3v example c: v os epad programmed at v in = +5v v supply = 5v cmrr = 80db three examples of equivalent input offset voltage due to change in common mode voltage vs. common mode voltage -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 common mode voltage (v) 50 40 30 20 10 0 equivalent input offset voltage due to change in common mode voltage ( v) v os epad programmed at common mode voltage of 0.25v cmrr = 80db example of minimizing equivalent input offset voltage for a common mode voltage range of 0.5v common mode voltage range of 0.5v
ald2726e/ald2726 advanced linear devices 9 total input v os after epad programming + device input v os psrr equivalent v os cmrr equivalent v os t a equivalent v os noise equivalent v os external error equivalent v os x example a total input offset voltage ( v) 2500 2000 1500 1000 500 0 -500 -1000 -1500 -2000 -2500 v os budget before epad programming v os budget after epad programming + x example b total input offset voltage ( v) 2500 2000 1500 1000 500 0 -500 -1000 -1500 -2000 -2500 + x v os budget before epad programming v os budget after epad programming example c total input offset voltage ( v) 2500 2000 1500 1000 500 0 -500 -1000 -1500 -2000 -2500 + x v os budget before epad programming v os budget after epad programming example d total input offset voltage ( v) 2500 2000 1500 1000 500 0 -500 -1000 -1500 -2000 -2500 + x v os budget after epad programming v os budget before epad programming application specific / in-system programming examples of applications where accumulated total input offset voltage from various contributing sources is minimized under different sets of user-specified operating conditions
10 advanced linear devices ald2726e/ald2726 definitions and design notes: 1. initial input offset voltage is the initial offset voltage of the ald2726e/ald2726 operational amplifier when shipped from the factory. the device has been pre-programmed and tested for programmability. 2. offset voltage program range is the range of adjustment of user specified target offset voltage. this is typically an adjust- ment in either the positive or the negative direction of the input offset voltage from an initial input offset voltage. the input offset programming pins, ve1a/ve1b or ve2a/ve2b change the input offset voltages in thepositive or negative direction, for each of the amplifier a or b, respectively. user specified target offset voltage can be any offset voltage within this programming range. 3. programmed input offset voltage error is the final offset voltage error after programming when the input offset voltage is at target offset voltage. this parameter is sample tested. 4. total input offset voltage is the same as programmed input offset voltage, corrected for system offset voltage error. usu- ally this is an all inclusive system offset voltage, which also includes offset voltage contributions from input offset voltage, psrr, cmrr, tcv os and noise. it can also include errors introduced by external components, at a system level. pro- grammed input offset voltage and total input offset voltage is not necessarily zero offset voltage, but an offset voltage set to compensate for other system errors as well. this parameter is sample tested. 5. the input offset and bias currents are essentially input protection diode reverse bias leakage currents. this low input bias current assures that the analog signal from the source will not be distorted by it. for applications where source impedance is very high, it may be necessary to limit noise and hum pickup through proper shielding. 6. input voltage range is determined by two parallel comple- mentary input stages that are summed internally, each stage having a separate input offset voltage. while total input offset voltage can be trimmed to a desired target value, it is essential to note that this trimming occurs at only one user selected input bias voltage. depending on the selected input bias voltage relative to the power supply voltages, offset voltage trimming may affect one or both input stages. for the ald2726e/ ald2726 , the switching point between the two stages occur at approximately 1.5v below positive supply voltage. 7. input offset voltage drift is the average change in total input offset voltage as a function of ambient temperature. this parameter is sample tested. 8. initial psrr and initial cmrr specifications are provided as reference information. after programming, error contribution to the offset voltage from psrr and cmrr is set to zero under the specific power supply and common mode conditions, and becomes part of the programmed input offset voltage error. 9. average long term input offset voltage stability is based on input offset voltage shift through operating life test at 125 c extrapolated to t a = 25 c, assuming activation energy of 1.0ev. this parameter is sample tested. additional design notes: a. the ald2726e/ald2726 is internally compensated for unity gain stability using a novel scheme which produces a single pole role off in the gain characteristics while providing more than 60 degrees of phase margin at unity gain frequency. a unity gain buffer using the ald2726e/ald2726 will typically drive 25pf of external load capacitance. b. the ald2726e/ald2726 has complementary p-channel and n-channel input differential stages connected in parallel to accomplish rail-to-rail input common mode voltage range. the switching point between the two differential stages is 1.5v below positive supply voltage. for applications such as inverting amplifier or non-inverting amplifier with a gain larger than 2.5 (5v operation), the common mode voltage does not make excursions below this switching point. however, this switching does take place if the operational amplifier is connected as a rail- to-rail unity gain buffer and the design must allow for input offset voltage variations. c. the output stage consists of class ab complementary output drivers. the oscillation resistant feature, combined with the rail- to-rail input and output feature, makes the ald2726e/ ald2726 an effective analog signal buffer for high source impedance sensors, transducers, and other circuit networks. d. the ald2726e/ald2726 has static discharge protection. care must be exercised when handling the device to avoid strong static fields that may degrade a diode junction, causing increased input leakage currents. the user is advised to power up the circuit before, or simultaneously with, any input voltages applied and to limit input voltages not to exceed 0.3v of the power supply voltage levels. e. vexx are high impedance terminals, as the internal bias currents are set very low to a few microamperes to conserve power. for some applications, these terminals may need to be shielded from external coupling sources. for example, digital signals running nearby may cause unwanted offset voltage fluctuations. care during the printed circuit board layout to place ground traces around these pins and to isolate them from digital lines will generally eliminate such coupling effects. in addition, optional decoupling capacitors of 1000pf or greater value can be added to vexx terminals. f. the ald2726e/ald2726 is designed for use in low voltage, micropower circuits. the maximum operating voltage during normal operation should remain below 10 volts at all times. care should be taken to insure that the application in which the device is used do not experience any positive or negative transient voltages that will cause any of the terminal voltages to exceed this limit. g. all inputs or unused pins except vexx pins should be connected to a supply voltage such as ground so that they do not become floating pins, since input impedance at these pins is very high. if any of these pins are left undefined, they may cause unwanted oscillation or intermittent excessive current drain. as these devices are built with cmos technology, normal operating and storage temperature limits, esd and latchup handling precautions pertaining to cmos device handling should be observed.
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